Periodic digital signals are commonly used in a variety of electronic devices. Probably the most common type of periodic digital signals are clock signals that are typically used to establish the timing of a digital signal or the timing at which an operation is performed on a digital signal. For example, in synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and it performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors.
The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, commands and addresses are placed on respective command and address buses of the memory device in synchronism with the external clock signal, and the memory device uses the external clock signal to latch these commands and addresses at the proper times to successfully capture the commands and addresses. Similarly, write data are applied to a data bus in synchronism with a write data strobe signal, and the memory device uses the write data strobe signal to latch the write data at the proper time.
Internal circuitry in a memory device through which the external clock and strobe signals are coupled necessarily introduces some time delay, causing the clock and strobe signals to be phase shifted by the time they reach respective latches. As long as the phase-shift is minimal relative to the timing margins of the memory device, the external clock and strobe signals can capture the commands, addresses and data at the proper time. However, as the operating speeds of memory devices have continued to increase, the “eyes” during which the commands, addresses and data must be captured have become increasingly smaller, thus making the timing of the clock and strobe signals even more critical. As a result, the time delays introduced by internal circuitry have become more significant.
To latch the applied commands, addresses, and write data at higher operating speeds, internal clock and strobe signals are developed in synchronism with the external clock and strobe signal, respectively. The internal clock signal is applied to latches contained in the memory device to thereby clock the commands and addresses into the latches during an “eye” in which the commands and addresses are valid. Similarly, the internal write data strobe signal is used to capture the write data in a latch at the proper time to ensure that a transition of the internal write data strobe signal occurs during an “eye” in which the write data are valid. A similar technique is often used in a memory controller coupled to a synchronous memory device. In such case, the memory device transmits read data and a read data strobe to the memory controller. The memory controller uses an internal read data strobe signal synchronized to the external read data strobe signal to capture the read data during the “eye” when the read data are valid.
A number of different approaches have been considered and utilized to generate internal clock and strobe signals that are synchronized to external clock and strobe signals, respectively. For example, delay-locked loops (DLLs), phased-locked loops (PLLs), measure controlled delays (MCDs), and synchronous mirror delays (“SMDs”) have been used, as will be appreciated by those skilled in the art. FIG. 1 is a functional block diagram of a conventional MCD 100 that receives an applied clock signal CLK and generates a clock signal CLKSYNC that is synchronized with the CLK signal. The MCD 100 includes an input buffer 102 that receives the CLK and generates a buffered clock signal CLKBUF in response to the CLK signal. The CLKBUF signal has a delay D1 relative to the CLK signal, where D1 corresponds to the inherent propagation delay of the input buffer.
A model delay line 104 receives the CLKBUF signal and generates a forward delay clock signal FDCLK having a model delay D1+D2 relative to the CLKBUF signal. The model delays D1 and D2 simulate the delay D1 introduced by the input buffer 102 and a delay D2 introduced by an output buffer 106 that generates the CLKSYNC signal, as will be explained in more detail below. The FDCLK signal propagates through a measuring delay line 108 including a plurality of delay units 110A-N coupled in series, each delay unit 11-A-N receiving an input signal from the prior delay unit generates an output signal having a delay UD relative to the input signal. Each delay unit 110A-N may, for example, be an AND gate having one input enabled as indicated for the delay unit 110A, with the inverter introducing the delay unit UD corresponding to the propagation delay of the inverter. In the measuring delay line 108, the FDCLK signal propagates through the delay units 110A-N from left to right in FIG. 1, as indicated by the orientation of the inverter in the delay unit 110A. Each of the delay units 110A-N generates a corresponding control signal on lines 112A-N, respectively. As the FDCLK signal propagates through the delay units 110A-N, a control signal at the corresponding output 112A-N changes state.
A signal generating delay line 114 includes a plurality of delay units 116A-N coupled in series as previously described for the measuring delay line 108. Instead of providing the outputs from the delay units 116A-N as with the measuring delay line 108, however, the signal generating delay line 114 has a plurality of inputs 118A-N to the corresponding delay unit 116A-N, respectively. Once again, each delay unit 116A-N may be formed by an AND gate. A controller 120 receiving the CLKBUF signal is coupled to receive the control signals on lines 112A-N of the measuring delay line 108. The controller 120 then outputs the CLKBUF signal on one of the inputs 118A-N of the delay units 116A-N in the signal generating delay line 114. The controller 120 uses the control signals from the measuring delay line 108 to determine the delay units 110A-N through which the rising edge of the FDCLK signal propagated by the time the next rising edge of the CLKBUF signal is received. The controller 120 then applies the CLKBUF signal to the input 118A-N of the delay unit 116A-N in the signal generating delay line 114 that corresponds to the delay unit 110A-N in the measuring delay line 108 to which the FDCLK signal had propagated. For example, if the rising edge of the FDCLK signal has propagated to the output of the delay unit 110J by the time the next rising edge of the CLKBUF signal is received, the controller 120 applies the CLKBUF signal to the input of the delay unit 116J in the signal generating delay line 114. The CLKBUF signal then propagates through the corresponding delay unit 116J in the signal generating delay line 114 and through all delay units 116I-A to the left of that delay unit, and is output from the signal generating delay line 114 as a delayed clock signal CLKDEL. The output buffer 106 receives the CLKDEL signal and generates the CLKSYNC in response to the CLKDEL signal, with the CLKSYNC being delayed by the delay D2 introduced by the output buffer.
The overall operation of the MCD 100 in synchronizing the CLKSYNC signal with the CLK signal will now be described in more detail with reference to FIG. 1 and a signal timing diagram of FIG. 2 illustrating various signals generated by the MCD during operation. In the example of FIG. 2, an initial rising-edge of the CLK signal occurs at time T0. In response to the rising-edge of the CLK signal at the time T0, the input buffer 102 drives the CLKBUF signal high with a delay D1 at time T1. This initial rising-edge of the CLKBUF signal is designated in FIG. 2 the N edge of the CLKBUF signal. In response to the rising-edge transition of the CLKBUF signal at the time T1, the model delay line 104 drives the FDCLK signal high after a model delay D1+D2 at time T2. The FDCLK signal thereafter propagates through the delay units 110A-N in the measuring delay line 108 until a next rising-edge N+1 of the CLKBUF signal is applied to the measuring delay line 108 at a time T3. At the time T3, the measuring delay line 108 has delayed the FDCLK signal by a delay FD that equals TCK−(D1+D2) where TCK is the period of the CLK signal. This is true because, as illustrated in FIG. 2, the next rising-edge of the CLKBUF signal occurs TCK−(D1+D2) after the initial rising-edge of the FDCLK signal at the time T2.
In response to the rising-edge of the CLKBUF signal at the time T3, the controller 120 applies the CLKBUF signal to the input of the delay unit 116A-N in the signal generating delay line that corresponds to the delay unit 110A-N to which the FDCLK signal had propagated when the rising edge of the CLKBUF signal was received. For example, assume that the delay TCK−(D1+D2) equals eleven delay units UD so that the controller 120 receives the control signal from the output 112K of the delay unit 110K in the measuring delay line 108. In this situation, the controller 120 applies the CLKBUF signal to the input 118K of the delay unit 116K in the signal generating delay line 114. This is illustrated in FIG. 2 as a rising-edge of the CLKBUF signal at the time T3.
The CLKBUF thereafter propagates through the appropriate delay units 116J-A in the signal generating delay line 114, and at a time T4 the signal generating delay line 114 drives the CLKDEL signal high in response to the applied output signal. At the time T4, the signal generating delay line 114 has delayed the CLKBUF by a delay that equals TCK−(D1+D2) which equals the delay FD of the measuring delay line 108. This is true because the CLKBUF signal propagates through the same number of delay units 116A-N in the signal generating delay line 114 as did the FDCLK signal propagate through the delay units 110A-N in the measuring delay line 108, as will be appreciated by those skilled in the art. The total delay of the CLKDEL signal at the time T4 equals D1+D1+D2+TCK−(D1+D2)+TCK−(D1+D2), which equals 2TCK-D2. Thus, the rising-edge of the CLKDEL signal at the time T4 occurs the delay D2 of the output buffer 106 before a next rising-edge of the CLK signal at a time T5. In response to the CLKDEL signal at the time T4, the output buffer 106 drives the CLKSYNC signal high at the time T5 and in synchronism with the rising-edge of the CLK signal. In this way, the MCD 100 generates the CLKSYNC signal having rising-edges that are synchronized with the rising-edges of the CLK signal.
In the MCD 100, although the input buffer 102 and output buffer 106 are illustrated as single components, each represents all components and the associated delays between the input and output of the MCD 100. The input buffer 106 thus represents the delay D1 of all components between an input that receives the CLK signal and the input to the model delay line 104, and the output buffer 106 represents the delay D2 of all components between the output of the signal generating delay line 114 and an output at which the CLKSYNC signal is developed, as will be appreciated by those skilled in the art.
As explained above, the controller 120 performs the function of applying the CLKBUF signal to one of the inputs 118A_N of the corresponding delay unit 116A-N in the signal generating delay line 114. As mentioned above, the controller 120 generally performs this function by detecting which delay units 110A-N in the measuring delay line 108 are outputting a high logic level when the next rising edge of the CLKBUF signal occurs. However, if the FDCLK signal simply propagated through the delay units 110A-N, the first half of the delay units 110A-N would be outputting a low logic level and the second half of the delay units 110A-N would be outputting a high logic level on the occurrence of the next rising edge of the CLKBUF signal. The mix of high and low logic levels from the delay units 110A-N would be even more complicated if, as in some MCDs, several periods of the FDCLK signal are allowed to propagate through the measuring delay line 108.
The mix of high and low logic levels that the controller 120 receives from the measuring delay line 108 can make it difficult for the controller 120 to perform its function of applying the CLKBUF signal to the correct delay unit 116A-N in the signal generating delay line 114. For this reason, MCDs typically include a control circuit (not shown) inserted between the model delay line 104 and the measuring delay line 108 for maintaining the FDCLK signal high responsive to the rising edge of the FDCLK signal. As a result, all of the delay units 110A-N through which the rising edge of the FDCLK signal propagates will output a high regardless of how many periods of the FDCLK signal have occurred during such time. Unfortunately, these control circuits inevitably delay the signal applied to the measuring delay line 108 responsive to the rising edge of the FDCLK signal. At higher operating speeds, these delays must be compensated for with a delay model, but such delay models do not always provide adequate compensation particularly in the presence of temperature, process and supply voltage variations.
The results achieved with the above-described control circuits, i.e., ensuring that all of the delay units 110A-N through which the rising edge of the FDCLK signal propagates output a high, could be achieved without using a control circuit by making the measuring delay line responsive to the falling edge of the CLKBUF signal. However, this approach would provide accurate results only if the falling edge of the FDCLK signal occurs after one-half period of the FDCLK signal. Unfortunately, external clock and strobe signals often do not have a 50% duty cycle. Therefore, this approach cannot be used in many cases.
There is therefore a need for an MCD having a measuring delay line that, for the entire period of an input signal, outputs high logic levels from all delay units 110A-N through which a transition of an input signal propagates without passing the input signal through a control circuit that introduces undesirable delays to the input signal.